Brian Kelleher
26Patents
14h-index
26Co-inventors
81Inventor score
Filing activity: Nov 24, 1987 → Oct 20, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6938176B1 | Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle | Emerging Cross-Sectional Technologies | 154 | Expired |
| US5794016A | Parallel-processor graphics architecture | Physics | 148 | Expired |
| US5287438A | System and method for drawing antialiased polygons | Physics | 98 | Expired |
| US6088043A | Scalable graphics processor architecture | Physics | 78 | Expired |
| US7721118B1 | Optimizing power and performance for multi-processor graphics processing | Emerging Cross-Sectional Technologies | 69 | Expired |
| US7598958B1 | Multi-chip graphics processing unit apparatus, system, and method | Physics | 67 | Expired |
| US7882369B1 | Processor performance adjustment system and method | Emerging Cross-Sectional Technologies | 57 | Expired |
| US7372465B1 | Scalable graphics processing for remote display | Physics | 52 | Expired |
| US4953101A | Software configurable memory architecture for data processing system having graphics capability | Physics | 41 | Expired |
| US7633505B1 | Apparatus, system, and method for joint processing in graphics processing units | Physics | 30 | Expired |
| US7005871B1 | Apparatus, system, and method for managing aging of an integrated circuit | Physics | 28 | Expired |
| US4935880A | Method of tiling a figure in graphics rendering system | Physics | 18 | Expired |
| US5008838A | Method for simultaneous initialization of a double buffer and a frame buffer | Physics | 17 | Expired |
| US7710741B1 | Reconfigurable graphics processing system | Electricity | 15 | Active |
| US5206628A | Method and apparatus for drawing lines in a graphics system | Physics | 12 | Expired |
| US8249819B1 | Virtual binning | Physics | 8 | Active |
| US5218678A | System and method for atomic access to an input/output device with direct memory access | Physics | 6 | Expired |
| US8130227B2 | Distributed antialiasing in a multiprocessor graphics system | Physics | 6 | Active |
| US8427496B1 | Method and system for implementing compression across a graphics bus interconnect | Electricity | 5 | Active |
| US9176909B2 | Aggregating unoccupied PCI-e links to provide greater bandwidth | Physics | 4 | Active |
| US9529712B2 | Techniques for balancing accesses to memory having different memory types | Emerging Cross-Sectional Technologies | 3 | Active |
| US11182309B2 | Techniques for an efficient fabric attached memory | Physics | 3 | Active |
| US8701057B2 | Design, layout, and manufacturing techniques for multivariant integrated circuits | Electricity | 1 | Active |
| US9477597B2 | Techniques for different memory depths on different partitions | Physics | 0 | Active |
| US11822491B2 | Techniques for an efficient fabric attached memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.