Automatic cache flush with readable and writable cache tag memory
US5287481A · kind A · utility
89Cited by
10References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 1992 |
| Grant date | Feb 15, 1994 |
| Priority date | — |
| Expiry date | May 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.