Polishing pad and method for polishing semiconductor wafers
US5287663A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1992 |
| Grant date | Feb 22, 1994 |
| Priority date | — |
| Expiry date | Apr 28, 2012 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B37/22
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A polishing pad and a method for polishing semiconductor wafers. The polishing pad includes a polishing layer and a rigid layer. The rigid layer adjacent the polishing layer imparts a controlled rigidity to the polishing layer. The resilient layer adjacent the rigid layer provides substantially uniform pressure to the rigid layer. During operation, the rigid layer and the resilient layer apply an elastic flexure pressure to the polishing layer to induce a controlled flex in the polishing layer to conform to the global topography of the wafer surface while maintaining a controlled rigidity over the local topography of the wafer surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.