Multi-chip stacked devices
US5291061A · kind A · utility
217Cited by
5References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 6, 1993 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Apr 6, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.