Semiconductor memory cell and memory array with inversion layer
US5291439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1991 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Sep 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.