Combination DRAM and SRAM memory array
US5291444A · kind A · utility
65Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1991 |
| Grant date | Mar 1, 1994 |
| Priority date | — |
| Expiry date | Dec 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.