Pseudo-Random scan test apparatus
US5293123A · kind A · utility
22Cited by
24References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1992 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Sep 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a circuit configuration that permits the monitoring of the operation of an input/output circuit of a digital unit under test by pseudo-random scan test techniques. A resistive element couples test signals to an input/output terminal of the device under test to which the input/output circuit is connected. The connection between the resistive element and the terminal is monitored during pseudo-random scan testing, permitting testing of the input/output circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.