Peter Fu
15Patents
7h-index
25Co-inventors
66Inventor score
Filing activity: Apr 16, 1987 → Jan 24, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10510396B1 | Method and apparatus for interrupting memory bank refresh | Emerging Cross-Sectional Technologies | 34 | Active |
| US5293123A | Pseudo-Random scan test apparatus | Physics | 22 | Expired |
| US4843608A | Cross-coupled checking circuit | Physics | 19 | Expired |
| US5032983A | Entry point mapping and skipping method and apparatus | Physics | 15 | Expired |
| US5539890A | Microprocessor interface apparatus having a boot address relocator, a request pipeline, a prefetch queue, and an interrupt filter | Physics | 8 | Expired |
| US6397315B1 | Processor interface chip for dual-microprocessor processor system | Physics | 7 | Expired |
| US7523342B1 | Data and control integrity for transactions in a computer system | Electricity | 7 | Active |
| US10545701B1 | Memory arbitration techniques based on latency tolerance | Physics | 7 | Active |
| US5590337A | Processor interface chip for dual-microprocessor processor system | Physics | 4 | Expired |
| US6654942B2 | Method and system for providing a netlist driven integrated router in a non-netlist driven environment | Physics | 3 | Expired |
| US10777252B2 | System and method for performing per-bank memory refresh | Physics | 2 | Active |
| US5778171A | Processor interface chip for dual-microprocessor processor system | Physics | 2 | Expired |
| US5435001A | Method of state determination in lock-stepped processors | Physics | 2 | Expired |
| US11221798B2 | Write/read turn techniques based on latency tolerance | Physics | 1 | Active |
| US7062611B2 | Dirty data protection for cache memories | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.