High density EEPROM cell with tunnel oxide stripe
US5293331A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1992 |
| Grant date | Mar 8, 1994 |
| Priority date | — |
| Expiry date | Jun 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
Abstract
An electrically erasable programmable read only memory (EEPROM) cell and fabrication process includes first field oxide regions (FOX1) formed in a P-well in an N-substrate to define a p-type device region. Buried N+ bit lines formed in the substrate adjacent to FOX1 regions define a p-channel region. Second field oxide (FOX2) regions overlying the N+ bit lines. A gate oxide layer is formed on the substrate between the FOX2 regions. A tunnel stripe is then defined in the gate oxide; the gate oxide is etched from the stripe; and a tunnel oxide stripe is grown in the etched stripe. The tunnel oxide stripe extends across a plurality of EEPROM cells sharing common bit lines. A layer of polysilicon is formed extending over the tunnel oxide stripe, thus defining a floating gate for the cell. The intersection of the tunnel oxide stripe and the floating gate defines the tunneling region for each cell. A layer of oxide/nitride/oxide (ONO) composite is formed over the floating gate. A second polysilicon layer and an overlying tungsten silicide are then formed over the ONO to define the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.