Method for manufacturing an EPROM cell
US5296397A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1993 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Apr 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate. The coupling efficiency between the control gate and the floating gate is primarily determined by the thickness of the first insulating film, which allows the second insulating film to be thicker to insure against current leakage from the floating gate and at the same time easier to deposit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.