Methods and devices for accelerating failure of marginally defective dielectric layers
US5297087A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1993 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Apr 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of row lines, a plurality of column lines, and a common storage cell plate. The memory device also includes a cell plate generator which produces a reference voltage. The reference voltage is connected to the common storage cell plate. A row decoder connects a row line voltage to selected individual row lines. A stress mode detection circuit receives a row line stress voltage and generates a stress mode signal in response. The row decoder is responsive to the stress mode signal to simultaneously bias all of the row lines to the row line stress voltage. At least one equilibrate circuit is also connected to receive the stress mode signal and is responsive to the stress mode signal to bias the column lines to the reference voltage. The memory device is furthermore responsive to the stress mode signal to ground the reference voltage. The circuits described create a voltage stress differential between the column lines, the row lines, and the common storage cell plate. This voltage stress differential is greater than any voltage differential occurring between the row lines, the column lines, and the storage cell plate during normal memor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.