Nonvolatile semiconductor memory device and data erasing method thereof
US5297096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1991 |
| Grant date | Mar 22, 1994 |
| Priority date | — |
| Expiry date | Jun 7, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.