Forming a device dielectric on a deposited semiconductor having sub-layers
US5298436A · kind A · utility
43Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1993 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Jun 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.