GTO thyristor capable of preventing parasitic thyristors from being generated

US5298769A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Ichiro Omura · Zürich, CH
• Mitsuhiko Kitagawa · Tokyo, JP

Key dates

• Filing date: Mar 31, 1993
• Grant date: Mar 29, 1994
• Expiry date: Mar 31, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D18/251

Abstract

A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET. A thyristor having such a configuration can effectively prevent a latched-up condition caused by parasitic transistors or thyristors to ensure turn off operations of the host thyristor.