Versatile and efficient cell-to-local bus interface in a configurable logic array
US5298805A · kind A · utility
84Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1993 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Apr 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.