Decoder scheme for fully associative translation-lookaside buffer
US5299147A · kind A · utility
45Cited by
1References
20Claims
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Key dates
| Filing date | Feb 22, 1993 |
| Grant date | Mar 29, 1994 |
| Priority date | — |
| Expiry date | Feb 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fully associative translation lookaside buffer (TLB) using a content addressable memory (CAM) array to store virtual addresses and a static random access memory (SRAM) array to store corresponding physical addresses. The TLB incorporates a logic circuit that allows the SRAM to be accessed during both associative and non-associative modes by word lines that are strictly a function of corresponding match lines. Additionally, the logic circuit incorporated in the TLB does not introduce any additional delay in outputting the physical address from the SRAM during the associative mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.