Semiconductor wafer with improved step coverage along scribe lines
US5300816A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jun 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02164
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas. The wafer includes a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of the integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions, wherein the peripheral edge portion of each multilayer structure has a multi-tiered cross-sectional profile, thereby ensuring adequate step coverage of the photoresist film which is applied to the individual layers of the multilayer structures when they are patterned during the wafer fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.