Semiconductor memory
US5301142A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 8, 1992 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jun 8, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.