Static random access memory cell with single logic-high voltage level bit-line and address-line drivers
US5301147A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1993 |
| Grant date | Apr 5, 1994 |
| Priority date | — |
| Expiry date | Jan 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory cell according to the present invention comprises first and second cross-coupled inverters. The first inverter includes a first P-Channel MOS transistor having a source connected to a first power supply node, a gate, and a drain, and a first N-Channel MOS transistor having a drain connected to the drain of the first P-Channel MOS transistor and forming an output node, a gate, and a source connected to a fixed power supply potential. The second inverter includes a second P-Channel MOS transistor having a source connected to the first power supply node, a gate, and a drain, and a second N-Channel MOS transistor having a drain connected to the drain of the second P-Channel MOS transistor, a gate, and a source connected to the fixed power supply potential. The gates of the first P-Channel and N-Channel MOS transistors are connected to the common drains of the second P-Channel and N-Channel MOS transistors and the gates of the second P-Channel and N-Channel MOS transistors are connected to the common drains of the first P-Channel and N-Channel MOS transistors to form the cross coupling connections. A pass transistor is connected between the output node of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.