Method for planarizing the surface of an integrated circuit over a metal interconnect layer

US5302551A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Ali A. Iranmanesh · Federal Way, US
• John M. Pierce · Clarkston, US

Key dates

• Filing date: May 11, 1992
• Grant date: Apr 12, 1994
• Expiry date: May 11, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76819
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is provided for planarizing the surface of an integrated circuit over a metal interconnect layer. Metal interconnect lines and surrounding regions of a partially fabricated integrated circuit are first coated with a thin layer of dielectric substantially free of voids and then coated with a polysilicon layer. The polysilicon layer is planarized back to the level of the dielectric layer on top of the interconnects, providing a substantially planar surface for subsequent fabrication steps including deposition of a second dielectric layer and an overlying metal layer.