Semiconductor heterostructure having a capping layer preventing deleterious effects of As-P exchange
US5302847A · kind A · utility
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7Claims
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Key dates
| Filing date | Jun 4, 1993 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Jun 4, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A III-V semiconductor heterojunction in which a capping layer (14) is formed between the two layers (10, 16) of the heterojunction to prevent any deleterious effects due to As-P exchange. When InAlAs is grown on InP, the capping layer is AlP. When GaAs is grown on GaInP, the capping layer is GaP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.