High-speed memory with a limiter of the drain voltage of the cells
US5303189A · kind A · utility
16Cited by
6References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1991 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Mar 1, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable and electrically programmable memory with only few cells works at high speed in reading mode and is reliable. This is achieved by using a voltage limiter that limits the variation in the drain voltage of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.