Paged memory controller
US5303364A · kind A · utility
39Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1992 |
| Grant date | Apr 12, 1994 |
| Priority date | — |
| Expiry date | Dec 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.