On chip decoupling capacitor
US5304506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1993 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Mar 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof. The second decoupling capacitor could be fabricated over field oxide and used as a single capacitor having a first and second conductively doped polysilicon electrodes (either silicided or non-silicided) with a capacitor dielectric sandwiched in between.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.