Semiconductor memory device having word line selection logic circuits
US5305279A · kind A · utility
6Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1992 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Mar 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to word line selection logic circuits for a semiconductor memory device composed of a plurality of memory blocks. Word line selection logic circuits are composed of groups of word line blocks, and semiconductors for switches operated by an output signal from a block selection decoder to activate a selected word line block. The switches are assigned to each block, and one of the word lines within the memory blocks is selected by supplying the activated word line block with an output signal from a row decoder which ensures improvement in access time and high density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.