Dram column address latching technique
US5305283A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1991 |
| Grant date | Apr 19, 1994 |
| Priority date | — |
| Expiry date | Apr 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and a method for latching a column address in a DRAM, having increased speed and no race conditions. The method is comprised of the steps of receiving column select and column address input signals, enabling detection and indication, by generation of an indication signal, of the presence of each stable column address input signal upon the presence of a column select signal, summing the indication signals, and operating a latch by each of the column address input signals whereby a DRAM column can be addressed upon enabling by the summed indication signals, whereby the latching is not enabled without a first indication of the presence of a stable column address and whereby the first indication is prevented without the earlier presence of a column select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.