Method for optimizing automatic place and route layout for full scan circuits
US5307286A · kind A · utility
10Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1992 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Dec 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.