Interlocked on-chip ECC system
US5307356A · kind A · utility
41Cited by
14References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1990 |
| Grant date | Apr 26, 1994 |
| Priority date | — |
| Expiry date | Apr 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line is used to signal the ECC when data from the DRAM arrays is valid during a fetch operation; the same dummy data line also signals the DRAM arrays when the data from the ECC is valid during a write-back operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.