Fabrication of electronic devices by electroless plating of copper onto a metal silicide
US5308796A · kind A · utility
62Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1993 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Apr 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.