Integrated circuit package having stress reducing recesses
US5309026A · kind A · utility
43Cited by
2References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1992 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Nov 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device has reduced stress concentration on the IC chip for prevention of package cracks in the device. Recessed portions are formed in the package at positions corresponding to at least the corner portions of the IC chip to reduce the stress concentration generated at the corner portions of the IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.