Synchronous processor unit with interconnected, separately clocked processor sections which are automatically synchronized for data transfer operations
US5309561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | May 3, 1994 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.