Method of integrated circuit fabrication including selective etching of silicon and silicon compounds
US5310457A · kind A · utility
17Cited by
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7Claims
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Key dates
| Filing date | Sep 30, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Sep 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
High etch selectivity of both silicon nitride and silicon with respect to silicon oxide is obtained using an etch bath of phosphoric acid, hydrofluoric acid, and nitric acid. Minimal loading effects are observed and a long bath life is obtained by replenishing the hydroflouric and nitric acids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.