Lead-on-chip semiconductor device and method for making the same
US5311057A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 1992 |
| Grant date | May 10, 1994 |
| Priority date | — |
| Expiry date | Nov 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead-on-chip (LOC) semiconductor device (10) has an integral decoupling capacitor in the form of a capacitor tape (20) attached to an active surface (14) of a semiconductor die (12). The capacitor tape includes two adhesive layers (22 and 24) to bond the die to the capacitor tape and to a plurality of leads (18). The tape also includes two conductive layers (26 and 28), made for instance of copper foil, which serve as the two electrodes of the capacitor. The electrodes are separated by a dielectric layer (30) which in one embodiment comprises barium-titanate (BaTiO.sub.3). The electrodes of the capacitor are electrically coupled to appropriate power and ground leads of the device by bonding wires (36 and 40) and to appropriate bonding pads (16) also by bonding wires (38 and 42). The bonding wires can be configured using any of three available wiring options. The present invention can also be implemented in a chip-on-lead (COL) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.