Capacitor and a memory cell formed therefrom
US5313089A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | May 26, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.