Semiconductor memory and memorizing method to read only semiconductor memory
US5313418A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Oct 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mask ROM of the invention comprises: a plurality of memory cells arranged m a matrix; a plurality of word lines, each connecting gates of the memory cells in the lateral direction; a plurality of bit lines which are constructed by serially connecting MOS transistors constructing the memory cells; a row decoder connected to the word lines; and a column decoder connected to the bit lines in which each memory cell is constructed by an MOS transistor and a resistor connected in parallel between the source and drain of each MOS transistor. The content of each memory cell is determined by whether the resistor 8 is cut out or not so that the steps up to the cutting step of the resistors 8 can be standardized while maintaining a high density in integration of the memory cells and the turn-around time can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.