Module level electronic redundancy
US5313424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1992 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Mar 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.