Boundary-scan input cell for a clock pin
US5313470A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1991 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | Sep 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A boundary-scan circuit for a system clock input pin of an integrated circuit which prevents the transmission of undesirable pulses into the clock inputs of the core logic circuits during switching to or from the test clock. This is accomplished by synchronizing the signal that controls the switching from or to the system clock to provide such switching during the inactive portion of the system clock cycle. The boundary-scan circuit uses plural switching elements to provide sufficient current drive to prevent degradation of a rise time of any clock pulse transmitted thereby without the use of additional current buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.