Switch queue structure for one-network parallel processor systems
US5313649A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1991 |
| Grant date | May 17, 1994 |
| Priority date | — |
| Expiry date | May 28, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/552
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switch queue structure for one-network parallel processor systems minimizes chip count and reduces the possibility of deadlock which might otherwise occur with this type of switch structure. The switch queue structure comprises a plurality of input ports and a plurality of output ports equal in number to a number of processor/memory elements (PMEs) in a parallel processor system. A plurality of identical stages interconnect the plurality of input ports and the plurality of output ports. Each stage includes a plurality of first groups of first-in, first-out (FIFO) registers storing request messages, a plurality of second groups of first-in, first-out registers storing response messages, and a plurality of multiplexers. Each of the multiplexers have inputs connected to the FIFO registers in each of the first and second groups for routing responses to memory requests from addressed processor/memory elements to requesting processor/memory elements and for routing memory requests from processor/memory elements to addressed processor/memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.