High performance trench EEPROM cell
US5315142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1992 |
| Grant date | May 24, 1994 |
| Priority date | — |
| Expiry date | Mar 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.