High-voltage five-transistor static random access memory cell
US5315545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1993 |
| Grant date | May 24, 1994 |
| Priority date | — |
| Expiry date | Jun 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V.sub.SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V.sub.SS. The gates of the first and second P-Channel MOS transistors are cross-coupled and the gates of the second and fourth N-Channel MOS transistors are cross-coupled. The gates of the first and third N-Channel MOS transistors are connected together to power supply rail V.sub.DD, u…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.