Method of decreasing the field oxide etch rate in isolation technology
US5316965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1993 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Jul 29, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process for planarizing an isolation barrier in the fabrication of a semiconductor chip involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with HF, the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.