Crater prevention technique for semiconductor processing
US5316976A · kind A · utility
16Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Jul 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor fabrication process is provided which prevents the cratering of the bond pads of an integrated circuit by including in a semiconductor process an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.