Apparatus and method for real time data error capture and compression redundancy analysis
US5317573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Feb 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fail information from testing of a DUT memory array is captured and compressed by utilizing a compression matrix which is related in size to the available redundancy associated with the DUT (device under test) memory array, and which, in essence, defines the limits of redundancy repair. The compression matrix includes a plurality of matrix cells fewer in number than the number of memory cells in the DUT memory array and is arranged in a matrix of compression rows and compression columns, the number R of compression rows in the compression matrix being equal to (a predetermined number of redundant rows in the memory array) times (a predetermined number of redundant memory columns+1), and the number C of compression columns in the compression matrix being equal to (a predetermined number of redundant memory columns) times (a predetermined number of redundant memory rows+1). The compression matrix is loaded with the fail information concurrently with testing of the DUT memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.