Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics
US5317715A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Jul 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.