Semiconductor package having an exposed die surface
US5319242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Mar 18, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a die having a first surface including a plurality of bond pads disposed thereon and a second surface. Inner lead portions of a TAB leadframe are coupled to the bond pads and outer lead portions electrically coupled to the inner lead portions extend therefrom. An encapsulation is disposed on the first surface of the die including the bond pads having the inner lead portions of the TAB leadframe bonded thereto. Encapsulation is also disposed about the sides of the die. The second surface of the die remains exposed. This allows for a relatively thin package having superior thermal dissipation properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.