Blocked flash write in dynamic RAM devices
US5319606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1992 |
| Grant date | Jun 7, 1994 |
| Priority date | — |
| Expiry date | Dec 14, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) device that is selectively operable in a normal write mode, in a block write mode, or in a blocked flash write mode in accordance with a mode select signal. In the preferred embodiment, each column of a 512.times.512 DRAM is divided into eight superblocks of 64 columns, each superblock being in turn divided into eight blocks of 8 columns each. An address decoder decodes the most significant column address bits A8-A6 to provide a group select signal specifying a 64-bit superblock, the next most significant column address bits A5-A3 to provide a block select signal specifying a 8-bit block, and the least significant column address bits A2-A0 to provide a cell select signal specifying a particular column. In the normal write mode, data is written to the specified column in the specified block in the specified superblock. In the block write mode, the same data is simultaneously written to selected columns in the specified block in the specified superblock. In the blocked flash write mode, the same data is simultaneously written to selected blocks in the specified superblock. An 8-bit data input line (D7-D0) is used to provide bits that select colum…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.