Multichip module having a stacked chip arrangement
US5323060A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1993 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Jun 2, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip module includes: a) a multichip module substrate; b) a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads peripheral to the central area; c) a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; d) a first/second adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the first/second adhesive layer having a thickness and a perimeter, the perimeter being positioned within the central area inside of the peripheral bonding pads; e) a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first bonding wires having outwardly projecting loops of a defined loop height, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires; and f) a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.