Integrated circuit memory with dual P-sense amplifiers associated with each column line
US5323350A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1992 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Aug 18, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM or VRAM integrated circuit memory of the divided bit line design includes a bit line pair extending from a column decoder to a SAM. An N-sense amplifier divides the bit line pair into two pairs of bit halves. The N-sense amplifier is connected to each of the bit line halves through an isolation transistor. A P-sense amplifier is connected across each pair of the bit line halves. Since a P-sense amplifier is associated with each pair of bit line halves, the P-sense amplifier never has to pull through isolation transistors, and thus the isolation transistors can be high threshold transistors, eliminating the natural threshold mask step in fabrication. The two P-sense amplifiers separate the bit line voltages faster, thereby decreasing crossing current and saving power, and pull the bit lines to full high voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.