Arrangement with self-amplifying dynamic MOS transistor storage cells

US5327374A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Krautschneider · Ottobrunn, DE
• Klaus J. Lau · South Burlington, US
• Lothar Risch · Neubiberg, DE

Key dates

• Filing date: Dec 29, 1992
• Grant date: Jul 5, 1994
• Expiry date: Dec 29, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An arrangement with self-amplifying dynamic MOS transistor storage cells has in each case a MOS selection transistor AT, whose gate is connected to a word line WL, and an MOS storage transistor ST at whose gate a capacitor C for charge storage acts. This self-amplifying storage cell can be written on and read out with only one bit line BL and one word line WL. The two transistors AT and ST are connected in series and a common drain source region DS is connected via a voltage-dependent resistor VR to the gate electrode GST of the control transistor. The advantages reside in the fact that the cell geometry can be scaled without at the same time the quantity Q of charge which can be read out on the bit line BL having to be reduced, in that the quantity Q of charge which can be read out is larger than a charge stored in the capacitor C which acts at the gate of the storage transistor ST and in that the two MOS transistors AT and ST can be produced relatively simply.