Redundancy selection apparatus and method for an array
US5327381A · kind A · utility
11Cited by
11References
11Claims
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Key dates
| Filing date | Jun 3, 1992 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Jun 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fused decoder for selecting one or more elements of an array, such as a row of memory, is provided. The corresponding row of memory can be permanently deselected by blowing the fuse of the decoder. Array components such as a redundant row of memory, can be substituted for the deselected component. The decoder includes a gate formed exclusively from NMOS transistors so that the decoder can provide a select signal in response to an address without an PMOS transistor responding to the address- By eliminating PMOS transistors from the gate portion of the decoder, the load presented to the address lines is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.